1. Technical Field
The present invention relates to an array substrate of a liquid crystal display device (LCD), and more particularly, to an array substrate having a polysilicon thin film transistor (TFT)-LCD which is fabricated using a diffraction exposure process, and a fabrication method thereof.
2. Description of the Related Art
Until recently, a cathode ray tube (CRT) has been most widely used among display devices for displaying image information on a screen. The CRT, however, has may inconveniences owing to a large volume and weight compared with the display area. To this end, a thin flat panel display has been developed that can be used anywhere, because it has a large display area and has a very thin profile. The flat panel display is now replacing the CRT. In particular, a liquid crystal display (LCD) exhibits higher resolution than other flat panel displays, and has a rapid response speed that is comparable to the display quality of the CRT when displaying moving images.
In operation, the LCD utilizes optical anisotropy and polarization. In other words, an alignment direction of the liquid crystal molecules is controllable by artificially applying an electromagnetic field to the liquid crystal molecules, which are thin and long in their structure and are directionally aligned.
The ability to artificially control their alignment direction allows the alignment direction of the liquid crystal molecules to be changed and the light that is polarized due to the optical anisotropy to can be modulated. Accordingly, the LCD is capable of displaying image information through the application of an electromagnetic field.
An active matrix liquid crystal display includes thin film transistors (TFTs) and pixel electrodes connected with the TFTs that are arranged in a matrix configuration. The active matrix LCD is being widely used due to its high resolution and superior moving picture reproduction capability.
A base element of the LCD is the liquid crystal panel, which will now be described with reference to the accompanying drawing.
FIG. 1 is a partial exploded perspective view of a typical LCD. In general, an LCD 11 includes an upper substrate 5 and a lower substrate 22. The upper substrate 5 includes a black matrix layer 6, a color filter layer 7, including sub-color filters of red (R), green (G) and blue (B), and a transparent common electrode 18 formed on the color filter layer 7. The lower substrate 22 includes pixel regions (P), pixel electrodes 17 formed on the pixel regions (P) and an array interconnection line including switching elements (T). Between the upper substrate 5 and the lower substrate 22, there is interposed a liquid crystal layer 15, described above.
The lower substrate 22 is known in the art as an “array substrate.” On the lower substrate 22, a plurality of thin film transistors that function as switching elements are arranged in a matrix configuration, and gate lines 13 and data lines 15 are formed to cross the plurality of thin film transistors. Also, the pixel regions (P) are defined by the crossing pattern of the gate lines 13 and the data lines 15.
The pixel electrode 17 formed on the pixel region (P) is made of a transparent conductive material having a superior light transmittance such as indium-tin-oxide. (ITO).
The LCD 11 configured as described above, displays images when the liquid crystal molecules of the liquid crystal layer 14 on the pixel electrode 17 are aligned by a signal applied via the thin film transistors. The liquid crystal molecules are aligned in such a way as to control the amount of light passing through the liquid crystal layer 14.
FIG. 2 is a partially magnified plan view of some pixels of a related art LCD array substrate. The array substrate employs a p-Si TFT. In other words, TFTs employed in LCDs are classified into amorphous silicon (a-Si) TFTs and polycrystalline silicon (p-Si) TFTs depending on crystalline state of the semiconductor layer serving as an active channel.
In a p-Si TFT, the driving frequency of a driving circuit that determines the number of the driving pixels can be advantageously enhanced and thus high definition capability is possible because the TFT has high field effect mobility. Also, in the p-Si TFT, enhanced picture quality can be expected because the charge time of a signal voltage to the pixel regions is reduced and thus distortion of transfer signals is reduced. Further, the p-Si TFT has an advantage of low power consumption because it can be driven at a voltage less than 10 V, compared with the a-Si TFT, which has a relatively higher driving voltage (about 25V).
Referring to FIG. 2, a plurality of gate lines 111 and a plurality of orthogonal data lines 112 are arranged in a matrix configuration, thereby defining pixel regions (P).
At cross points of the data lines 112 and the gate line 111, the TFTs (T) each include a semiconductor layer 116, a gate electrode 120, a source electrode 126 and a drain electrode 128, and pixel electrodes 134 electrically connected with the TFTs.
The semiconductor layer 116 is electrically connected with the source electrode 126 and the drain electrode 128 through first and second semiconductor layer contact holes 122a and 122b, and the drain electrode 128 is electrically connected with the pixel electrode 134 through a drain contact hole 130.
The semiconductor layer 116 is formed by depositing an amorphous (a-Si) film on the substrate and crystallizing the deposited a-Si film using laser annealing to form polycrystalline silicon.
FIGS. 3A through 3G are sectional views schematically illustrating a process flow to obtain the LCD array substrate of FIG. 2, in which the sectional views are taken along the line A I-I′ of FIG. 2. In the process shown in FIGS. 3A through 3G, an array substrate employing a p-Si TFT is used, and respective patterns are formed by transferring patterns of a mask onto a substrate having a thin film formed thereon. For example, a photolithography process is used that includes photoresist coating, mask alignment, exposure of the photoresist through the mask, and development of the photoresist.
Referring to FIG. 3A, a buffer layer 30 is formed on the entire surface of an insulating substrate 1 using a first insulating material, and a polysilicon active layer 32a is then formed on the buffer layer 30 using a first mask process.
The active layer 32a is formed by depositing an amorphous silicon layer on the buffer layer 30, performing dehydrogenation of the amorphous silicon layer, and crystallizing the amorphous silicon layer into polysilicon layer by a heat treatment.
Referring to FIG. 3B, after the process of FIG. 3A, a second insulating material and a first metal film are sequentially deposited and patterned by a second mask process to form a gate insulating layer 36 and a gate electrode 38 at a middle portion of the active layer 32a (shown in FIGS. 3D and 3E).
Also, to form a channel region and a heavily impurity-doped source and drain regions in the active layer 32a, both exposed edges of the active layer 32a are ion-doped using the gate electrode 38 as a mask.
Referring to FIG. 3C, after the process of FIG. 3B, a first insulating layer 40 is formed of a third insulating material on a resultant structure of the substrate 1.
Referring to FIG. 3D, after the process of FIG. 3C, a third insulating material is deposited and then patterned by a third mask process to form a second insulating layer 44 having first and second ohmic contact holes 46a and 46b that partially expose both edges of the active layer 32a. Alternatively, the first and second insulating layers 40 and 44 may be formed as a single layer.
In both edges of the active layer 32a, the left edge is a source region 1a connected with a source electrode to be formed by a subsequent process and the right edge is a drain region 1b to be connected with a drain electrode. Next, both exposed edges of the active layer 32a are heavily doped with impurity ions to form ohmic contact layers 32b and 32c. 
Next, referring to FIG. 3E, a third metal film is deposited and then patterned by a fourth mask process to form a drain electrode 50 and a source electrode 52. At this time, the drain electrode 50 is connected with the ohmic contact layer 32c of the drain region Ib through the first ohmic contact hole (46a of FIG. 3D), and the source electrode 52 is connected with the ohmic contact layer 32b of the source region Ia through the second ohmic contact hole (46b of FIG. 3D).
In this process, a TFT (T) is formed that includes the semiconductor layer 32, the gate electrode 38, and the source and drain electrodes 52 and 50. The gate electrode 38 is connected with the gate line (not shown), and the source electrode 52 is connected with the data line (not shown).
Next, referring to FIG. 3F, after the process of FIG. 3E, a fourth insulating material is deposited on a resultant structure of the substrate 1 and then patterned by a fifth mask process to form a third insulating layer 54 having a drain contact hole 56.
Next, referring to FIG. 3G, an indium tin oxide (ITO) transparent conductive layer is deposited on a resultant structure of the substrate 1 including the drain contact hole 56 and then patterned by a sixth mask process to form a pixel electrode 62. The indium tin oxide forms a low resistance contact with a metal when a TAB bonded.
As described above, the related art LCD array substrate is fabricated by six masking steps.
The respective mask processes represent a series of processes for forming a desired pattern in a thin film formed on a substrate. Each masking process transfers a pattern of a mask onto the thin film and includes the steps of photoresist coating, exposure, and developing, and the like.
As the number of the mask processes increases, production yield is lowered and the probability of incurring defects is increased. Also, since masks designed for forming patterns are very expensive, the increase in the number of the masks used in the fabrication of the array substrate increases the fabrication costs of the LCD.